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1/40 MSM80C154s/83c154s ? semiconductor general description the MSM80C154s/msm83c154s, designed for the high speed version of the existing MSM80C154/msm83c154, is a higher performance 8-bit microcontroller providing low-power consumption. the MSM80C154s/msm83c154s covers the functions and operating range of the existing MSM80C154/83c154/80c51f/80c31f. the MSM80C154s is identical to the msm83c154s except it does not contain the internal program memory (rom). features ? operating range operating frequency : 0 to 3 mhz (v cc =2.2 to 6.0 v) 0 to 12 mhz (v cc =3.0 to 6.0 v) 0 to 24 mhz (v cc =4.5 to 6.0 v) operating voltage : 2.2 to 6.0 v operating temperature : C40 to +85 c (operation at +125 c conforms to the other specification.) ? fully static circuit ? upward compatible with the msm80c51f/80c31f ? on-chip program memory : 16k words x 8 bits rom (msm83c154s only) ? on-chip data memory : 256 words x 8 bits ram ? external program memory address space : 64k bytes rom (max) ? external data memory address space : 64k bytes ram ? i/o ports : 4 ports x 8 bits (port 1, 2, 3, impedance programmable) : 32 ? 16-bit timer/counters : 3 ? multifunctional serial port : i/o expansion mode : uart mode (featuring error detection) ? 6-source 2-priority level interrupt and multi-level interrupt available by programming ip and ie registers ? memory-mapped special function registers ? bit addressable data memory and sfrs ? minimum instruction cycle : 500 ns @ 24 mhz operation ? standby functions : power-down mode (oscillator stop) activated by software or hardware; providing ports with floating or active status the software power-down stet mode is termi- nated by interrupt signal enabling execution from the interrupted address. ? semiconductor MSM80C154s/83c154s cmos 8-bit microcontroller e2e1023-27-y3 this version: jan. 1998 previous version: nov. 1996
2/40 MSM80C154s/83c154s ? semiconductor ? package options 40-pin plastic dip (dip40-p-600-2.54) : (product name: MSM80C154srs/ msm83c154s-xxxrs) 44-pin plastic qfp (qfp44-p-910-0.80-2k) : (product name: MSM80C154sgs-2k/ msm83c154s-xxxgs-2k) 44-pin qfj (qfj44-p-s650-1.27) : (product name: MSM80C154sjs/ msm83c154s -xxx js) 44-pin tqfp (tqfp44-p-1010-0.80-k) : (product name: MSM80C154sts-k/ msm83c154s-xxxts-k) xxx: indicates the code number
3/40 MSM80C154s/83c154s ? semiconductor t2con pch control signal special function register address decoder pla ir air c-rom tr1 tr2 acc alu br psw ramdp r/w amp ram 256 words x 8bits th2 rcap2h rcap2l dph pcl sp rom 16k words x 8bits sense amp dpl pcll port 2 port 0 pcon iocon osc and timing port 1 port 3 p2.0 p2.7 p0.0 p0.7 p1.0 p1.7 p3.0 p3.7 xtal1 xtal2 ale reset psen ea th1 tl1 th0 tl0 tmod tcon ie ip sbuf(t) sbuf(r) interrupt timer/counter 0 & 1 serial io scon signal r/w timer/ counter 2 pchl address decoder tl2 block diagram (msm83c154s)
4/40 MSM80C154s/83c154s ? semiconductor pin configuration (top view) 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 v ss p1.0/t2 p1.1/t2ex p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 reset p3.0/rxd p3.1/txd p3.2/ int0 p3.3/ int1 p3.4/t0 p3.5/t1/hpdi p3.6/ wr p3.7/ rd xtal2 xtal1 p2.0 v cc p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 ea ale psen p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 21 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 40-pin plastic dip
5/40 MSM80C154s/83c154s ? semiconductor 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 p1.5 p1.6 p1.7 reset p3.0/rxd nc p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1/hpdi p0.4 p0.5 p0.6 p0.7 ea nc ale psen p2.7 p2.6 p2.5 44 43 42 41 40 39 38 37 36 35 34 p1.4 p1.3 p1.2 p1.1 p1.0 nc v cc p0.0 p0.1 p0.2 p0.3 12 13 14 15 16 17 18 19 20 21 22 p3.6/wr p3.7/rd xtal2 xtal1 v ss v ss p2.0 p2.1 p2.2 p2.3 p2.4 nc : no-connection pin 44-pin plastic qfp pin configuration (continued)
6/40 MSM80C154s/83c154s ? semiconductor 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 p1.5 p1.6 p1.7 reset p3.0/rxd nc p3.1/txd p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1/hpdi p0.4 p0.5 p0.6 p0.7 ea nc ale psen p2.7 p2.6 p2.5 44 43 42 41 40 39 38 37 36 35 34 p1.4 p1.3 p1.2 p1.1 p1.0 nc v cc p0.0 p0.1 p0.2 p0.3 12 13 14 15 16 17 18 19 20 21 22 p3.6/wr p3.7/rd xtal2 xtal1 v ss v ss p2.0 p2.1 p2.2 p2.3 p2.4 nc : no-connection pin 44-pin plastic tqfp
7/40 MSM80C154s/83c154s ? semiconductor pin configuration (continued) nc : no-connection pin 44-pin plastic qfj p0.3 p0.2 p0.1 p0.0 v cc nc p1.0/t2 p1.1/t2ex p1.2 p1.3 p1.4 p2.3 p2.2 p2.1 p2.0 nc v ss xtal1 xtal2 p3.7/ rd p3.6/ wr p1.5 p1.6 p1.7 reset p3.0/rxd nc p3.1/txd p3.2/ int0 p3.3/ int1 p3.4/t0 p0.5 p0.6 p0.7 ea nc ale psen p2.7 p2.6 p2.5 p0.4 p2.4 p3.5/t1/hpdi 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 28 27 26 25 24 23 22 21 20 19 18 39 38 37 36 35 34 33 32 31 30 29
8/40 MSM80C154s/83c154s ? semiconductor p0.0 to p0.7 p1.0 to p1.7 p2.0 to p2.7 p3.0 to p3.7 ale psen ea symbol descriptipn bidirectional i/o ports. they are also the data/address bus (input/output of data and output of lower 8-bit address when external memory is accessed). they are open-drain outputs when used as i/o ports, but 3-state outputs when used as data/address bus. p1.0 to p1.7 are quasi-bidirectional i/o ports. they are pulled up internally when used as input ports. two of them have the following secondary functions: ?p1.0 (t2) ?p1.1 (t2ex) : used as external clock input pins for the timer/counter 2. : used as trigger input for the timer/counter 2 to be reloaded or captured; causing the timer/counter 2 interrupt. p2.0 to p2.7 are quasi-bidirectional i/o ports. they also output the higher 8-bit address when an external memory is accessed. they are pulled up internally when used as input ports. p3.0 to p3.7 are quasi-bidirectional i/o ports. they are pulled up internally when used as input ports. they also have the following secondary functions: ?p3.0 (rxd) serial data input/output in the i/o expansion mode and serial data input in the uart mode when the serial port is used. ?3.1 (txd) synchronous clock output in the i/o expansion mode and serial data output in the uart mode when the serial port is used. ?3.2 ( int0 ) used as input pin for the external interrupt 0, and as count-up control pin for the timer/counter 0. ?3.3 ( int1 ) used as input pin for the external interrupt 1, and as count-up control pin for the timer/counter 1. ?3.4 (t0) used as external clock input pin for the timer/counter 0. ?3.5 (t1) used as external clock input pin for the timer/counter 1 and power-down-mode control input pin. ?3.6 ( wr ) output of the write-strobe signal when data is written into external data memory. ?3.7 ( rd ) output of the read-strobe signal when data is read from external data memory. address latch enable output for latching the lower 8-bit address during external memory access. two ale pulses are activated per machine cycle except during external data memory access at which time one ale pulse is skipped. program store enable output which enables the external memory output to the bus during external program memory access. two psen pulses are activated per machine cycle except during external data memory access at which two psen pulses are skipped. when ea is held at "h" level, the msm 83c154s executes instructions from internal program memory at address 0000h to 3fffh, and executes instructions from external program memory above address 3fffh. when ea is held at "l" level, the MSM80C154s/msm83c154s executes instructions from external program memory for all addresses. pin descriptions
9/40 MSM80C154s/83c154s ? semiconductor pin descriptions (continued) reset symbol descriptipn xtal1 xtal2 v cc v ss if this pin remains "h" for at least one machine cycle, the MSM80C154s/msm83c154s is reset. since this pin is pulled down internally, a power-on reset is achieved by simply connecting a capacitor between v cc and this pin. oscillator inverter input pin. external clock is input through xtal1 pin. oscillator inverter output pin. power supply pin during both normal operation and standby operations. gnd pin.
10/40 MSM80C154s/83c154s ? semiconductor registers diagram of special function registers register name bit address direct address b7 b5 b4 b3 b2 b1 b0 b6 iocon b acc psw th2 tl2 rcap2h rcap2l t2con ip p3 ie p2 sbuf scon p1 th1 th0 tl1 tl0 tmod tcon pcon dph dpl sp p0 ff f7 e7 d7 cf bf b7 af a7 9f 97 8f 87 fe f6 e6 d6 ce be b6 ae a6 9e 96 8e 86 fd f5 e5 d5 cd bd b5 ad a5 9d 95 8d 85 fc f4 e4 d4 cc bc b4 ac a4 9c 94 8c 84 fb f3 e3 d3 cb bb b3 ab a3 9b 93 8b 83 fa f2 e2 d2 ca ba b2 aa a2 9a 92 8a 82 f9 f1 e1 d1 c9 b9 b1 a9 a1 99 91 89 81 f8 f0 e0 d0 c8 b8 b0 a8 a0 98 90 88 80 0f8h (248) 0f0h (240) 0e0h (224) 0d0h (208) 0cdh (205) 0cch (204) 0cbh (203) 0cah (202) 0c8h (200) 0b8h (184) 0b0h (176) 0a8h (168) 0a0h (160) 99h (153) 98h (152) 90h (144) 8dh (141) 8ch (140) 8bh (139) 8ah (138) 89h (137) 88h (136) 87h (135) 83h (131) 82h (130) 81h (129) 80h (128)
11/40 MSM80C154s/83c154s ? semiconductor timer/counter 0 mode setting name address msb lsb 76543210 bit location flag function tmod 89h gate c/ t m1 m0 gate c/ t m1 m0 tmod.0 m0 m1 m0 8-bit timer/counter with 5-bit prescalar. 00 16-bit timer/counter. 01 8-bit timer/counter with 8-bit auto reloading. 10 timer/counter 0 separated into tlo (8-bit) timer/counter and th0 (8-bit) timer/counter. tf0 is set by tl0 carry, and tf1 is set by th0 carry. 11 tmod.1 m1 timer/counter 0 count clock designation control bit. xtal1?2 divided by 12 clocks is the input applied to timer/counter 0 when c/ t = "0". the external clock applied to the t0 pin is the input applied to timer/counter 0 when c/ t = "1". tmod.2 c/ t when this bit is "0", the tr0 bit of tcon (timer control register) is used to control the start and stop of timer/counter 0 counting. if this bit is "1", timer/counter 0 starts counting when both the tr0 bit of tcon and int0 pin input signal are "1", and stops counting when either is changed to "0". tmod.3 gate timer/counter 1 mode setting tmod.4 m0 m1 m0 8-bit timer/counter with 5-bit prescalar. 00 16-bit timer/counter 01 8-bit timer/counter with 8-bit auto reloading. 10 timer/counter 1 operation stopped. 11 tmod.5 m1 timer/counter 1 count clock designation control bit. xtal1?2 divided by 12 clocks is the input applied to timer/counter 1 when c/ t = "0". the external clock applied to the t1 pin is the input applied to timer/counter 1 when c/ t = "1". tmod.6 c/ t when this bit is "0", the tr1 bit of tcon is used to control the start and stop of timer/counter 1 counting. if this bit is "1", timer/counter 1 starts counting when both the tr1 bit of tcon and int1 pin input signal are "1", and stops counting when either is changed to "0". tmod.7 gate special function registers timer mode register (tmod)
12/40 MSM80C154s/83c154s ? semiconductor power control register (pcon) idle mode is set when this bit is set to "1". cpu operations are stopped when idle mode is set, but xtal1?2, timer/counters 0, 1 and 2, the interrupt circuits, and the serial port remain active. idle mode is cancelled when the cpu is reset or when an interrupt is generated. name address msb lsb 76543210 bit location flag function pcon 87h smod hpd rpd gf1 gf0 pd idl pcon.0 idl pd mode is set when this bit is set to "1". cpu operations and xtal1?2 are stopped when pd mode is set. pd mode is cancelled when the cpu is reset or when an interrupt is generated. pcon.1 pd general purpose bit. pcon.2 gf0 general purpose bit. pcon.3 gf1 reserved bit. the output data is "1", if the bit is read. pcon.4 this bit is used to specify cancellation of cpu power down mode (idle or pd) by an interrupt signal. power-down mode cannot be cancelled by an interrupt signal if the interrupt is not enabled by ie (interrupt enable register) when this bit is "0". if the interrupt flag is set to "1" by an interrupt request signal when this bit is "1" (even if interrupt is disabled), the program is executed from the next address of the power-down-mode setting instruction. the flag is reset to "0" by software. pcon.5 rpd the hard power-down setting mode in enabled when this bit is set to "1". if the level of the power failure detect signal applied to the hpdi pin (pin 3.5) is changed from "1" to "0" when this bit is "1", xtal1?2 oscillation is stopped and the system is put into hard power down mode. hpd mode is cancelled when the cpu is reset. pcon.6 hpd when the timer/counter 1 carry signal is used as a clock in mode 1, 2 or 3 of the serial port, this bit has the following functions. the serial port operation clock is reduced by 1/2 when the bit is "0" for delayed processing. when the bit is "1", the serial port operation clock is normal for faster processing. pcon.7 smod
13/40 MSM80C154s/83c154s ? semiconductor external interrupt 0 signal is used in level-detect mode when this bit is "0" and in trigger detect mode when "1". name address msb lsb 76543210 bit location flag function tcon 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tcon.0 it0 interrupt request flag for external interrupt 0. the bit is reset automatically when an interrupt is serviced. the bit can be set and reset by software when it0 = "1". tcon.1 ie0 external interrupt 1 signal is used in level detect mode when this bit is "0", and in trigger detect mode when "1". tcon.2 it1 interrupt request flag for external interrupt 1. the bit is reset automatically when an interrupt is serviced. the bit can be set and reset by software when it1 = "1". tcon.3 ie1 counting start and stop control bit for timer/counter 0. timer/counter 0 starts counting when this bit is "1", and stops counitng when "0". tcon.4 tr0 interrupt request flag for timer interrupt 0. the bit is reset automatically when an interrupt is serviced. the bit is set to "1" when a carry signal is generated from timer/counter 0. tcon.5 tf0 counting start and stop control bit for timer/counter 1. the timer/counter 1 starts counting when this bit is "1", and stops counting when "0". tcon.6 tr1 interrupt request flag for timer interrupt 1. the bit is reset automatically when interrupt is serviced. the bit is set to "1" when carry signal is generated from timer/counter 1. tcon.7 tf1 timer control register (tcon)
14/40 MSM80C154s/83c154s ? semiconductor "end of serial port reception" interrupt request flag. this flag must be reset by software during interrupt service routine. this flag is set after the eighth bit of data has been received when in mode 0, or by the stop bit when in any other mode. in mode 2 or 3, however, ri is not set if the rb8 data is "0" with sm2 = "1". ri is set in mode 1 if stop bit is received when sm2 = "1". name address msb lsb 76543210 bit location flag function scon 98h sm0 sm1 sm2 ren tb8 rb8 ti ri scon.0 ri "end of serial port tramsmission" interrupt request flag. this flag must be reset by software during interrupt service routine. this flag is set after the eighth bit of data has been sent when in mode 0, or after the last bit of data has been sent when in any other mode. scon.1 ti the tb8 data is sent as the ninth data bit when in mode 2 or 3. any desired data can be set in tb8 by software. scon.3 tb8 scon.6 sm1 sm0 sm1 8-bit shift register i/o 00 8-bit uart variable baud rate 01 9-bit uart 1/32 xtal1, 1/64 xtal1 baud rate 10 9-bit uart variable baud rate 11 scon.7 sm0 the ninth bit of data received in mode 2 or 3 is passed to rb8. the stop bit is applied to rb8 if sm2 = "0" when in mode 1. rb8 can not be used in mode 0. scon.2 rb8 reception enable control bit. no reception when ren = "0". reception enabled when ren = "1". scon.4 ren if the ninth bit of received data is "0" with sm2 = "1" in mode 2 or 3, the "end of reception" signal is not set in the ri flag. the "end of reception" signal set in the ri flag if the stop bit is not "1" when sm2 = "1" in mode 1. scon.5 sm2 mode 0 1 2 3 serial port control register (scon)
15/40 MSM80C154s/83c154s ? semiconductor interrupt control bit for external interrupt 0. interrupt disabled when bit is "0". interrupt enabled when bit is "1". name address msb lsb 76543210 bit location flag function ie 0a8h ea et2 es et1 ex1 et0 ex0 ie.0 ex0 interrupt control bit for timer interrupt 0. interrupt disabled when bit is "0". interrupt enabled when bit is "1". ie.1 et0 interrupt control bit for external interrupt 1. interrupt disabled when bit is "0". interrupt enabled when bit is "1". ie.2 ex1 interrupt control bit for timer interrupt 1. interrupt disabled when bit is "0". interrupt enabled when bit is "1". ie.3 et1 interrupt control bit for serial port. interrupt disabled when bit is "0". interrupt enabled when bit is "1". ie.4 es interrupt control bit for timer interrupt 2. interrupt disabled when bit is "0". interrupt enabled when bit is "1". ie.5 et2 reserved bit. the output data is "1" if the bit is read. ie.6 overall interrupt control bit. all interrupts are disabled when bit is "0". all interrupts are controlled by ie.0 thru ie.5 when bit is "1". ie.7 ea interrupt enable register (ie)
16/40 MSM80C154s/83c154s ? semiconductor interrupt priority bit for external interrupt 0. priority is assigned when bit is "1". name address msb lsb 76543210 bit location flag function ip 0b8h pct pt2 ps pt1 px1 pt0 px0 ip.0 px0 ip.1 pt0 ip.2 px1 ip.3 pt1 ip.4 ps ip.5 pt2 reserved bit. the output data is "1" if the bit is read. ip.6 priority interrupt circuit control bit. the priority register contents are valid and priority assigned interrupts can be processed when this bit is "0". when the bit is "1", the priority interrupt circuit is stopped, and interrupts can only be controlled by the interrupt enable register (ie). ip.7 pct interrupt priority bit for timer interrupt 0. priority is assigned when bit is "1". interrupt priority bit for external interrupt 1. priority is assigned when bit is "1". interrupt priority bit for timer interrupt 1. priority is assigned when bit is "1". interrupt priority bit for serial port. priority is assigned when bit is "1". interrupt priority bit for timer interrupt 2. priority is assigned when bit is "1". interrupt priority register (ip)
17/40 MSM80C154s/83c154s ? semiconductor program status word register (psw) accumulator (acc) parity indicator. this bit is "1" when the "1" bit number in the accumulator is an odd number, and "0" when an even number. name address msb lsb 76543210 bit location flag function psw 0d0h cy ac f0 rs1 rs0 ov f1 p psw.0 p user flag which may be set to "0" or "1" as desired by the user. psw.1 f1 ram register bank switch psw.3 rs0 rs1 rs0 00h - 07h 00 08h - 0fh 01 10h - 17h 10 18h - 1fh 11 psw.4 rs1 overflow flag which is set if the carry c6 from bit 6 of the alu or cy is "1" as a result of an arithmetic operation. the flag is also set to "1" if the resultant product of executing multiplication instruction (mul ab) is greater than 0ffh, but is reset to "0" if the product is less than or equal to 0ffh. psw.2 ov bank 0 1 2 3 user flag which may be set to "0" or "1" as desired by the user. psw.5 f0 auxiliary carry flag. this flag is set to "1" if a carry c 3 is generated from bit 3 of the alu as a result of executing an arithmetic operation instruction. in all other cases, the flag is reset to "0". psw.6 ac main carry flag. this flag is set to "1" if a carry c 7 is generated from bit 7 of the alu as result of executing an arithmetic operation instruction. if a carry c 7 is not generated, the flag is reset to "0". psw.7 cy ram address
18/40 MSM80C154s/83c154s ? semiconductor if cpu power down mode (pd, hpd) is activated with this bit set to "1", the outputs from ports 0, 1, 2, and 3 are switched to floating status. when this bit is "0", ports 0, 1, 2, and 3 are in output mode. name address msb lsb 76543210 bit location flag function iocon 0f8h t32 serr izc p3hz p2hz p1hz alf iocon.0 alf iocon.1 p1hz iocon.2 p2hz iocon.3 p3hz iocon.4 izc iocon.5 serr timer/counters 0 and 1 are connected serially to from a 32-bit timer/counter when this bit is set to "1". tf1 of tcon is set if a carry is generated in the 32-bit timer/counter. iocon.6 t32 leave this bit at "0". iocon.7 port 1 becomes a high impedance input port when this bit is "1". port 2 becomes a high impedance input port when this bit is "1". port 3 becomes a high impedance input port when this bit is "1". the 10 k w pull-up resistor for ports 1, 2, and 3 is switched off when this bit is "1", leaving only the 100 k w pull-up resistor. serial port reception error flag. this flag is set to "1" if an overrun or framing error is generated when data is received at a serial port. the flag is reset by software. i/o control register (iocon)
19/40 MSM80C154s/83c154s ? semiconductor capture mode is set when tclk + rclk = "0" and cp/ rl2 = "1". 16-bit auto reload mode is set when tclk + rclk = "0" and cp/ rl2 = "0". cp/ rl2 is ignored when tclk + rclk = "1". name address msb lsb 76543210 bit location flag function t2con 0c8h tf2 exf2 rclk tclk exen2 tr2 c/ t2 cp/ rl2 t2con.0 cp/ rl2 t2con.1 c/ t2 t2con.2 tr2 t2con.3 exen2 t2con.4 tclk t2con.5 rclk timer/counter 2 external flag. this bit is set to "1" when the t2ex timer/counter 2 external control signal level is changed from "1" to "0" while exen2 = "1". this flag serves as the timer interrupt 2 request signal. if an interrupt is generated, exf2 must be reset to "0" by software. t2con.6 exf2 timer/counter 2 carry flag. this bit is set to "1" by a carry signal when timer/counter 2 is in 16-bit auto reload mode or in capture mode. this flag serves as the timer interrupt 2 request signal. if an interrupt is generated, tf2 must be reset to "0" by software. t2con.7 tf2 timer/counter 2 count clock designation control bit. the internal clocks (xtal1?2 12, xtal1?2 2) are used when this bit is "0", and the external clock applied to the t2 pin is passed to timer/counter 2 when the bit is "1". timer/counter 2 counting start and stop control bit. timer/counter 2 commences counting when this bit is "1" and stops counting when "0". t2ex timer/counter 2 external control signal control bit. input of the t2ex signal is disabled when this bit is "0", and enabled when "1". serial port transmit circuit drive clock control bit. timer/counter 2 is switched to baud rate generator mode when this bit is "1", and the timer/counter 2 carry signal becomes the serial port transmit clock. note, however, that the serial ports can only use the timer/counter 2 carry signal in serial port modes 1 and 3. serial port receive circuit drive clock control bit. timer/counter 2 is switched to baud rate generator mode when this bit is "1", and the timer/counter 2 carry signal becomes the serial port transmit clock. note, however, that the serial ports can only use the timer/counter 2 carry signal in serial port modes 1 and 3. timer 2 control register (t2con)
20/40 MSM80C154s/83c154s ? semiconductor memory maps program area 002bh 43 timer interrupt 2 start 0023h 35 s i/o interrupt start 001bh 27 timer interrupt 1 start 0013h 19 external interrupt 1 start 0001h 1 0000h 0 cpu reset start 0003h 3 external interrupt 0 start 0002h 2 000bh 11 timer interrupt 0 start 16384 65535 4000h 0ffffh msm83c154s external rom area 43 16383 002bh 3fffh msm83c154s internal rom area 44 002ch 7 6 5 4 3 2 1 0 0 MSM80C154s external rom area
21/40 MSM80C154s/83c154s ? semiconductor internal data memory and special function register layout diagram 248(0f8h) 240(0f0h) 224(0e0h) 208(0d0h) 205(0cdh) 204(0cch) 203(ocbh) 202(0cah) 200(0c8h) 184(0b8h) 176(0b0h) 168(0a8h) 160(0a0h) 153( 99h) 152( 98h) 144( 90h) 141( 8dh) 140( 8ch) 139( 8bh) 138( 8ah) 137( 89h) 136( 88h) 135( 87h) 131( 83h) 130( 82h) 129( 81h) 128( 80h) ffh~f8h f7h~f0h e7h~e0h d7h~d0h cfh~c8h bfh~b8h b7h~b0h afh~a8h a7h~a0h 9fh~98h 97h~90h 8fh~88h 87h~80h iocon b acc psw th2 tl2 rcap2h rcap2l t2con ip p3 ie p2 sbuf scon p1 th1 th0 tl1 tl0 tmod tcon pcon dph dpl sp p0 user data ram bit ram bank3 r7 r0 bank2 r7 r0 bank1 r7 r0 bank0 r7 r0 7f 7 78 0 1f 18 17 10 0f 08 07 00 2f 20 7f 30 80 hex 0ff register indirect addressing special function registers user data ram bit addressing data addressing
22/40 MSM80C154s/83c154s ? semiconductor 7f 77 6f 67 5f 57 4f 47 3f 37 2f 27 1f 17 0f 07 7e 76 6e 66 5e 56 4e 46 3e 36 2e 26 1e 16 0e 06 7d 75 6d 65 5d 55 4d 45 3d 35 2d 25 1d 15 0d 05 7c 74 6c 64 5c 54 4c 44 3c 34 2c 24 1c 14 0c 04 7b 73 6b 63 5b 53 4b 43 3b 33 2b 23 1b 13 0b 03 7a 72 6a 62 5a 52 4a 42 3a 32 2a 22 1a 12 0a 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 bank 2 bank 1 bank 0 bank 3 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 127 255 31 24 23 16 15 08h 7 0 2fh 2eh 2dh 2ch 2bh 2ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 7fh 0ffh 1fh 18h 17h 10h 0fh 07h 00h 8 register 0, 1, indirect addressing bit addressing data addressing registers 0-7 diriect addressing user data ram user data ram 48 128 30h 80h diagram of internal data memory (ram)
23/40 MSM80C154s/83c154s ? semiconductor absolute maximum ratings parameter symbol condition rating unit supply voltage input voltage storage temperature v cc ta=25c C0.5 to 7 v v i ta=25c C0.5 to v cc +0.5 v t stg C55 to +150 c recommended operating conditions parameter symbol condition range unit power supply voltage memory retension voltage oxcillation frequency v cc see below. 2.0 to 6.0 v v cc f osc =0 hz (oscillation stop) 2.0 to 6.0 v f osc see below. 1 to 24 mhz external clock operating frequency ambient temperature f extclk see below. 0 to 24 mhz ta C40 to +85 c *1 depends on the specifications for the oscillator or ceramic resonater. 12 5 4 3 2 1 0.5 23456 power supply voltage (v cc ) 12 6 3 1 2.2 0.6 24 20 t cy ( m s) f osc f extclk (mhz)
24/40 MSM80C154s/83c154s ? semiconductor electrical characteristics dc characteristics 1 meas- uring circuit 0.2 v cc C0.1 parameter symbol condition min. typ. max. unit input low voltage v il C0.5 v v cc +0.5 input high voltage v ih except xtal1, ea , 0.2 v cc +0.9 v and reset v cc +0.5 input high voltage v ih1 xtal1, reset and ea 0.7 v cc v 0.45 output low voltage v ol i ol =1.6 ma v (port 1, 2, 3) 0.45 output low voltage v ol1 i ol =3.2 ma v (port 0, ale, psen ) output high voltage v oh i oh =C60 m a 2.4 v (port 1, 2, 3) v cc =5 v10% i oh =C30 m a 0.75 v cc v i oh =C10 m a 0.9 v cc v output high voltage v oh1 i oh =C400 m a 2.4 v (port 0, ale, psen ) v cc =5 v10% i oh =C150 m a 0.75 v cc v i oh =C40 m a 0.9 v cc v C80 logical 0 input current/ logical 1 output current/ (port 1, 2, 3) i il / i oh v i =0.45 v C5 C20 m a v o =0.45 v C500 logical 1 to 0 transition i tl v i =2.0 v C190 m a output current (port 1, 2, 3) 125 reset pull-down resistance r rst 2040 k w 10 pin capacitance c io ta=25c, f=1 mhz pf (except xtal1) 50 power down current i pd 1 m a 1 2 2 4 3 10 input leakage current i li v ss < v i < v cc m a (port 0 floating, ea ) (v cc =4.0 to 6.0 v, v ss =0 v, ta=-40 to +85c)
25/40 MSM80C154s/83c154s ? semiconductor maximum power supply current normal operation i cc (ma) v cc 4 v 5 v 6 v freq 2.2 3.1 4.1 1 mhz 3.9 5.2 7.0 3 mhz 12.0 16.0 20.0 12 mhz 16.0 20.0 25.0 16 mhz 19.0 25.0 30.0 20 mhz v cc 4.5 v 5 v 6 v freq 25.0 29.0 35.0 24 mhz maximum power supply current idle mode i cc (ma) v cc 4 v 5 v 6 v freq 0.8 1.2 1.6 1 mhz 1.2 1.7 2.3 3 mhz 3.1 4.4 5.9 12 mhz 3.8 5.5 7.3 16 mhz 4.5 6.4 8.6 20 mhz v cc 4.5 v 5 v 6 v freq 6.4 7.4 9.8 24 mhz
26/40 MSM80C154s/83c154s ? semiconductor dc characteristics 2 output high voltage v oh1 i oh =C20 m a 0.75 v cc v (port 0, ale, psen ) C40 logical 0 input current/ logical 1 output current/ (port 1, 2, 3) i il / i oh v i =0.1 v C5 C10 m a v o =0.1 v C300 logical 1 to 0 transition i tl v i =1.9 v C80 m a output current (port 1, 2, 3) 125 reset pull-down resistance r rst 2040 k w 10 pin capacitance c io ta=25c, f=1 mhz pf (except xtal1) 10 power down current i pd 1 m a 2 2 4 3 10 input leakage current i li v ss < v i < v cc m a (port 0 floating, ea ) meas- uring circuit 0.25 v cc C0.1 parameter symbol condition min. typ. max. unit input low voltage v il C0.5 v v cc +0.5 input high voltage v ih except xtal1, ea , 0.25 v cc +0.9 v and reset v cc +0.5 input high voltage v ih1 xtal1, reset, and ea 0.6 v cc +0.6 v 0.1 output low voltage v ol i ol =10 m a v (port 1, 2, 3) 0.1 output low voltage v ol1 i ol =20 m a v (port 0, ale, psen ) output high voltage v oh i oh =C5 m a 0.75 v cc v (port 1, 2, 3) 1 (v cc =2.2 to 4.0 v, v ss =0 v, ta=-40 to +85c)
27/40 MSM80C154s/83c154s ? semiconductor maximum power supply current normal operation i cc (ma) v cc 2.2 v 3.0 v 4.0 v freq 0.9 1.4 2.2 1 mhz 1.8 2.4 4.3 3 mhz 8.0 12.0 12 mhz 16.0 16 mhz maximum power supply current idle mode i cc (ma) v cc 2.2 v 3.0 v 4.0 v freq 0.3 0.5 0.8 1 mhz 0.5 0.8 1.2 3 mhz 2.0 3.1 12 mhz 3.8 16 mhz
28/40 MSM80C154s/83c154s ? semiconductor v cc v ss input output v ih v il (*2) v a i o 1 v cc v ss input output (*1) v 2 v cc v ss input output v ih v il (*2) v a (*3) 3 v cc v ss input output v ih v il a 4 a (*3) (*3) measuring circuits *1: repeated for specified input pins. *2: repeated for specified output pins. *3: input logic for specified status.
29/40 MSM80C154s/83c154s ? semiconductor ac characteristics (1) external program memory access ac characteristics parameter symble unit min. max. 1 to 24 mhz variable clock from 41.7 1000 ns t clcl xtal1, xtal 2 oscillation cycle 2t clcl -40 ns t lhll ale signal width 1t clcl -15 ns t avll address setup time (to ale falling edge) 1t clcl -35 ns t llax address hold time (from ale falling edge) 4t clcl -100 ns t llpl instruction data read time (from ale falling edge) 1t clcl -30 ns t llpl from ale falling edge to psen falling edge 3t clcl -35 ns t plph psen signal width 3t clcl -45 ns t pliv instruction data read time (from psen falling edge) 0ns t pxix instruction data hold time (from psen rising edge) 1t clcl -20 ns t pxiz bus floating time after instruction data read (from psen rising edge) 5t clcl -105 ns t aviv instruction data read time (from address output) 0ns t azpl bus floating time( psen rising edge from address float) 1t clcl -20 ns t pxav address output time from psen rising edge *1 v cc =2.2 to 6.0v, v ss =0v, ta=C40c to +85c port 0, ale, and psen connected with 100pf load, other connected with 80pf load *1 the variable check is from 0 to 24 mhz when the external check is used.
30/40 MSM80C154s/83c154s ? semiconductor t lhll t avll t llpl t plph t lliv t pliv t pxav t pxiz t llax t azpl t aviv t pxix a0 to a7 instr in a0 to a7 port0 port2 a8 to a15 a8 to a15 a8 to a15 psen ale (2) external program memory read cycle
31/40 MSM80C154s/83c154s ? semiconductor (3) external data memory access ac characteristics *1 the variable check is from 0 to 24 mhz when the external check is used. *2 for 2.2 v cc <4 v parameter symbol unit min. max. 1 to 24 mhz variable clock from 41.7 1000 ns t clcl xtal1, xtal2 oscillator cycle 2t clcl -40 ns t lhll ale signal width 1t clcl -15 ns t avll address setup time (to ale falling edge) 1t clcl -35 ns t llax address hold time (from ale falling edge) 6t clcl -100 ns t rlrl rd signal width 6t clcl -100 ns t wlwh wr signal width 5t clcl -105 ns t rldv ram data read time (from rd signal falling edge) 0ns t rhdx ram data read hold time (from rd signal rising edge) 2t clcl -70 ns t rhdz data bus floating time (from rd signal rising edge) 8t clcl -100 ns t lldv ram data read time (from ale signal falling edge) 9t clcl -105 ns t avdv ram data read time (from address output) 3t clcl -40 3t clcl +40 ns t llwl rd / wr output time from ale falling edge 4t clcl -70 ns t avwl rd / wr output time from address output 1t clcl -40 ns t qvwx wr output time from data output 7t clcl -105 ns t qvwh time from data to wr rising edge 2t clcl -50 ns t whqx data hold time (from wr rising edge) 0ns t rlaz time from to address float rd output 1t clcl -30 1t clcl +40 ns t whlh time from rd / wr rising edge to ale rising edge *1 3t clcl -100 *2 *2 1t clcl +100 v cc =2.2 to 6.0v, v ss =0v, ta=C40c to +85c port 0, ale, and psen connected with 100pf load, other connected with 80pf load
32/40 MSM80C154s/83c154s ? semiconductor t lhll t whlh t lldv t llwl t rlrh t avll t llax t rldv t rhdx t rhdz t avwl t avdv pch a8 to a15 pch p2.0 to p2.7 data a8 to a15 dph or a8 to a15 pch a0 to a7 pcl a0 to a7 rr or dpl a0 to a7 pcl instr in ale psen rd port 0 port 2 data in t azrl t lhll t whlh t llwl t wlwh t avll t llax t qvwh t whqx t avwl a8 to a15 pch p2.0 to p2.7 data a8 to a15 dph or a8 to a15 pch a0 to a7 pcl a0 to a7 rr or dpl a0 to a7 pcl instr in ale psen wr port 0 port 2 data (acc) a8 to a15 pch t qvwx (4) external data memory read cycle (5) external data memory write cycle
33/40 MSM80C154s/83c154s ? semiconductor (6) serial port (i/o extension mode) ac characteristics parameter symbol min. max. unit serial port clock cycle time t xlxl 12t clcl ns output data setup to clock rising edge t qvxh 10t clcl -133 output data hold after clock rising edge t xhqx 2t clcl -75 input data hold after clock rising edge t xhdx 0 clock rising edge to input data valid t xhdv 10t clcl -133 ns ns ns ns (v cc =2.2 to 6.0v, v ss =0v, ta=C40c to +85c)
34/40 MSM80C154s/83c154s ? semiconductor t xlxl t qvxh t xhqx t xhdv t xhdx valid valid valid valid valid valid valid valid machine cycle ale shift clock output data input data
35/40 MSM80C154s/83c154s ? semiconductor (7) ac characteristics measuring conditions 1.input/output signal v oh v ol v oh v ol v ih v il v ih v il test point * the input signals in ac test mode are either v oh (logic "1") or v ol (logic "0") input signals where logic "1" corresponds to a cpu output signal waveform measuring point in excess of v ih , and logic "0" to a point below v il . 2.floating v oh v ol v oh v ol v ih v il v ih v il floating * the port 0 floating interval is measured from the time the port 0 pin voltage drops below v ih after sinking to gnd at 2.4 ma when switching to floating status from a "1" output, and from the time the port 0 pin voltage exceeds v il after connecting to a 400 m a source when switching to floating status from a "0" output. (8) xtal1 external clock input waveform conditions parameter symbol min. max. unit external clock freq. 1/t clcl 0 24 mhz clock pulse width 1 t chcx 15 clock pulse width 2 t clcx 15 rise time t clch 5 fall time t chcl 5 ns ns ns ns external clock drive waveform 0.7 v cc 0.2 v cc - 0.1 t chcl t clch t clcx t clcl t chcx external oscillator signal
36/40 MSM80C154s/83c154s ? semiconductor timing diagram basic timing acc & ram s1 s2 s3 s4 s5 s6 m1 s1 s2 s3 s4 s5 s6 m1 s1 s2 s3 s4 s5 s6 m2 s1 s2 s3 s4 s5 s6 m1 pcl pcl pcl pcl pch pch pch pch pch dph & port data pch pc+1 tm+1 pc+1 tm+1 tm+1 tm+1 pc+1 pc+1 pc+1 cycle step 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 xtal 1 ale rd / wr port-0 port-2 cpu ? port port ? cpu pch pcl dpl&rr data stable port old data data stable psen pcl port new data port output/input instruction execution instruction execution external data memory instruction execution instruction execution port output/input instruction execution instruction execution instruction decoding instruction decoding instruction decoding
37/40 MSM80C154s/83c154s ? semiconductor (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). dip40-p-600-2.54 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 6.10 typ.
38/40 MSM80C154s/83c154s ? semiconductor (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.41 typ. qfp44-p-910-0.80-2k mirror finish
39/40 MSM80C154s/83c154s ? semiconductor (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfj44-p-s650-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin cu alloy solder plating 5 m m or more 2.00 typ. mirror finish
40/40 MSM80C154s/83c154s ? semiconductor (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tqfp44-p-1010-0.80-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.28 typ. mirror finish

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